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Vol. 3 6-57
INTERRUPT AND EXCEPTION HANDLING
description for “Interrupt 10—Invalid TSS Exception (#TS)” in this chapter for addi-
tional information on how to handle this situation.)
Additional Exception-Handling Information
Special care should be taken to ensure that an exception that occurs during an
explicit stack switch does not cause the processor to use an invalid stack pointer
(SS:ESP). Software written for 16-bit IA-32 processors often use a pair of instruc
-
tions to change to a new stack, for example:
MOV SS, AX
MOV SP, StackTop
When executing this code on one of the 32-bit IA-32 processors, it is possible to get
a page fault, general-protection fault (#GP), or alignment check fault (#AC) after the
segment selector has been loaded into the SS register but before the ESP register
has been loaded. At this point, the two parts of the stack pointer (SS and ESP) are
inconsistent. The new stack segment is being used with the old stack pointer.
The processor does not use the inconsistent stack pointer if the exception handler
switches to a well defined stack (that is, the handler is a task or a more privileged
procedure). However, if the exception handler is called at the same privilege level
and from the same task, the processor will attempt to use the inconsistent stack
pointer.
In systems that handle page-fault, general-protection, or alignment check excep-
tions within the faulting task (with trap or interrupt gates), software executing at the
same privilege level as the exception handler should initialize a new stack by using
the LSS instruction rather than a pair of MOV instructions, as described earlier in this
note. When the exception handler is running at privilege level 0 (the normal case),
the problem is limited to procedures or tasks that run at privilege level 0, typically
the kernel of the operating system.