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Vol. 3 14-13
POWER AND THERMAL MANAGEMENT
Support for TM2 is indicated by CPUID.1:ECX.TM2[bit 8] = 1.
14.5.2.3 Two Methods for Enabling TM2
On processors with CPUID family/model/stepping signature encoded as 0x69n or
0x6Dn (early Pentium M processors), TM2 is enabled if the TM_SELECT flag (bit 16)
of the MSR_THERM2_CTL register is set to 1 (
Figure 14-6) and bit 3 of the
IA32_MISC_ENABLE register is set to 1.
Following a power-up or reset, the TM_SELECT flag may be cleared. BIOS is required
to enable either TM1 or TM2. Operating systems and applications must not disable
mechanisms that enable TM1 or TM2. If bit 3 of the IA32_MISC_ENABLE register is
set and TM_SELECT flag of the MSR_THERM2_CTL register is cleared, TM1 is
enabled.
On processors introduced after the Pentium 4 processor (this includes most Pentium
M processors), the method used to enable TM2 is different. TM2 is enable by setting
bit 13 of IA32_MISC_ENABLE register to 1. This applies to Intel Core Duo, Core Solo,
and Intel Core 2 processor family.
The target operating frequency and voltage for the TM2 transition after TM2 is trig-
gered is specified by the value written to MSR_THERM2_CTL, bits 15:0 (Figure 14-7).
Following a power-up or reset, BIOS is required to enable at least one of these two
thermal monitoring mechanisms. If both TM1 and TM2 are supported, BIOS may
choose to enable TM2 instead of TM1. Operating systems and applications must not
disable the mechanisms that enable TM1or TM2; and they must not alter the value in
bits 15:0 of the MSR_THERM2_CTL register.
Figure 14-6. MSR_THERM2_CTL Register On Processors with CPUID
Family/Model/Stepping Signature Encoded as 0x69n or 0x6Dn
TM_SELECT
Reserved
31
0
Reserved
16