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Vol. 3 1-3
ABOUT THIS MANUAL
The Intel
®
Core
TM
i7 processor and the Intel
®
Core
TM
i5 processor are based on the
Intel
®
microarchitecture (Nehalem) and support Intel 64 architecture.
Processors based on the Next Generation Intel Processor, codenamed Westmere,
support Intel 64 architecture.
P6 family, Pentium
®
M, Intel
®
Core™ Solo, Intel
®
Core™ Duo processors, dual-core
Intel
®
Xeon
®
processor LV, and early generations of Pentium 4 and Intel Xeon
processors support IA-32 architecture. The Intel
®
Atom
TM
processor Z5xx series
support IA-32 architecture.
The Intel
®
Xeon
®
processor 3000, 3200, 5000, 5100, 5200, 5300, 5400, 7100,
7200, 7300, 7400 series, Intel
®
Core™2 Duo, Intel
®
Core™2 Extreme processors,
Intel Core 2 Quad processors, Pentium
®
D processors, Pentium
®
Dual-Core
processor, newer generations of Pentium 4 and Intel Xeon processor family support
Intel
®
64 architecture.
IA-32 architecture is the instruction set architecture and programming environment
for Intel's 32-bit microprocessors. Intel
®
64 architecture is the instruction set archi-
tecture and programming environment which is a superset of and compatible with
IA-32 architecture.
1.2 OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE
A description of this manual’s content follows:
Chapter 1 — About This Manual. Gives an overview of all five volumes of the
Intel® 64 and IA-32 Architectures Software Developer’s Manual. It also describes
the notational conventions in these manuals and lists related Intel manuals and
documentation of interest to programmers and hardware designers.
Chapter 2 — System Architecture Overview. Describes the modes of operation
used by Intel 64 and IA-32 processors and the mechanisms provided by the architec-
tures to support operating systems and executives, including the system-oriented
registers and data structures and the system-oriented instructions. The steps neces
-
sary for switching between real-address and protected modes are also identified.
Chapter 3 — Protected-Mode Memory Management. Describes the data struc-
tures, registers, and instructions that support segmentation and paging. The chapter
explains how they can be used to implement a “flat” (unsegmented) memory model
or a segmented memory model.
Chapter 4 — Paging. Describes the paging modes supported by Intel 64 and IA-32
processors.
Chapter 5 — Protection. Describes the support for page and segment protection
provided in the Intel 64 and IA-32 architectures. This chapter also explains the
implementation of privilege rules, stack switching, pointer validation, user and
supervisor modes.