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8-38 Vol. 3
MULTIPLE-PROCESSOR MANAGEMENT
8.7 INTEL
®
HYPER-THREADING TECHNOLOGY
ARCHITECTURE
Figure 8-4 shows a generalized view of an Intel processor supporting Intel Hyper-
Threading Technology, using the original Intel Xeon processor MP as an example.
This implementation of the Intel Hyper-Threading Technology consists of two logical
processors (each represented by a separate architectural state) which share the
processor’s execution engine and the bus interface. Each logical processor also has
its own advanced programmable interrupt controller (APIC).
Figure 8-3. Local APICs and I/O APIC in MP System Supporting Intel HT Technology
I/O APIC
External
Interrupts
System Chip Set
Bridge
PCI
Interrupt Messages
Local APIC
Logical
Processor 0
Local APIC
Logical
Processor 1
Hyper-Threading Technology
Intel Processor with Intel
Bus Interface
Processor Core
IPIs
Interrupt
Messages
Local APIC
Logical
Processor 0
Local APIC
Logical
Processor 1
Hyper-Threading Technology
Intel Processor with Intel
Bus Interface
Processor Core
IPIs
Interrupt
Messages