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Vol. 3 10-1
CHAPTER 10
ADVANCED PROGRAMMABLE
INTERRUPT CONTROLLER (APIC)
The Advanced Programmable Interrupt Controller (APIC), referred to in the following
sections as the local APIC, was introduced into the IA-32 processors with the Pentium
processor (see
Section 19.27, “Advanced Programmable Interrupt Controller
(APIC)”) and is included in the P6 family, Pentium 4, Intel Xeon processors, and other
more recent Intel 64 and IA-32 processor families (see Section 10.4.2, “Presence of
the Local APIC”). The local APIC performs two primary functions for the processor:
• It receives interrupts from the processor’s interrupt pins, from internal sources
and from an external I/O APIC (or other external interrupt controller). It sends
these to the processor core for handling.
• In multiple processor (MP) systems, it sends and receives interprocessor
interrupt (IPI) messages to and from other logical processors on the system bus.
IPI messages can be used to distribute interrupts among the processors in the
system or to execute system wide functions (such as, booting up processors or
distributing work among a group of processors).
The external I/O APIC is part of Intel’s system chip set. Its primary function is to
receive external interrupt events from the system and its associated I/O devices and
relay them to the local APIC as interrupt messages. In MP systems, the I/O APIC also
provides a mechanism for distributing external interrupts to the local APICs of
selected processors or groups of processors on the system bus.
This chapter provides a description of the local APIC and its programming interface.
It also provides an overview of the interface between the local APIC and the I/O
APIC. Contact Intel for detailed information about the I/O APIC.
When a local APIC has sent an interrupt to its processor core for handling, the
processor uses the interrupt and exception handling mechanism described in
Chapter
6, “Interrupt and Exception Handling.” See Section 6.1, “Interrupt and Exception
Overview,” for an introduction to interrupt and exception handling.
10.1 LOCAL AND I/O APIC OVERVIEW
Each local APIC consists of a set of APIC registers (see Table 10-1) and associated
hardware that control the delivery of interrupts to the processor core and the gener-
ation of IPI messages. The APIC registers are memory mapped and can be read and
written to using the MOV instruction.
Local APICs can receive interrupts from the following sources:
• Locally connected I/O devices — These interrupts originate as an edge or
level asserted by an I/O device that is connected directly to the processor’s local