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Vol. 3 13-11
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND
The TS flag can be set either explicitly (by executing a MOV instruction to control
register CR0) or implicitly (using the IA-32 architecture’s native task switching mech-
anism). When the native task switching mechanism is used, the processor automati-
cally sets the TS flag on a task switch. After the device-not-available handler has
saved the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 state, it should execute the
CLTS instruction to clear the TS flag.
Figure 13-1 gives an example of an operating system that implements x87
FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 state saving using the TS flag. In this
example, task A is the currently running task and task B is the new task. The oper
-
ating system maintains a save area for the x87
FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 state for each task and defines a variable
(x87_MMX_SSE_SSE2_SSE3_StateOwner) that indicates the task that “owns” the
state. In this example, task A is the current owner.
On a task switch, the operating system task switching code must execute the
following pseudo-code to set the TS flag according to the current owner of the x87
FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 state. If the new task (task B in this
example) is not the current owner of this state, the TS flag is set to 1; otherwise, it is
set to 0.
IF Task_Being_Switched_To ≠ x87FPU_MMX_XMM_MXCSR_StateOwner
THEN
CR0.TS ← 1;
ELSE
CR0.TS ← 0;
FI;
Figure 13-1. Example of Saving the x87 FPU, MMX, SSE, SSE2, SSE3, and SSSE3
State During an Operating-System Controlled Task Switch
Task A
Task B
Application
Operating System
Task A
Operating System
Task Switching Code
Device-Not-Available
Exception Handler
Owner of x87 FPU,
CR0.TS=1 and x87 FPU
MMX, SSEx
Instruction is encountered
MMX, XMM,
x87 FPU/MMX/
State Save Area
XMM/MXCSR
Task B
x87 FPU/MMX/
State Save Area
XMM/MXCSR
Saves Task A
x87 FPU/MMX/
XMM/MXCSR State
Loads Task B
x87 FPU/MMX/
XMM/MXCSR State
MXCSR State