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4-46 Vol. 3
PAGING
4.10.3 Invalidation of TLBs and Paging-Structure Caches
As noted in Section 4.10.1 and Section 4.10.2, the processor may create entries in
the TLBs and the paging-structure caches when linear addresses are translated, and
it may retain these entries even after the paging structures used to create them have
been modified. To ensure that linear-address translation uses the modified paging
structures, software should take action to invalidate any cached entries that may
contain information that has since been modified.
4.10.3.1 Operations that Invalidate TLBs and Paging-Structure Caches
It is recommended that software use the following instructions to invalidate entries in
the TLBs and the paging-structure caches:
• INVLPG. This instruction takes a single operand, which is a linear address. The
instruction invalidates any TLB entries with a page number corresponding to the
linear address, including those for global pages (see Section 4.10.1.4).
1
INVLPG
also invalidates all entries in all paging-structure caches regardless of the linear
addresses to which they correspond.
• MOV to CR3. This instruction invalidates all TLB entries except those for global
pages. It also invalidates all entries in all paging-structure caches.
• MOV to CR4. If this instruction changes value of the PGE flag (bit 7) of CR4, it
invalidates all TLB entries and all entries in all paging-structure caches. This
includes global TLB entries because (1) if CR4.PGE is changing from 0 to 1, there
were no global TLB entries before the execution; and (2) if CR4.PGE is changing
from 1 to 0, there will be no global TLB entries after the execution.
• Task switch. If a task switch changes the value of CR3, it invalidates all TLB
entries except those for global pages. It also invalidates all entries in all paging-
structure caches.
• VMX transitions. See Section 4.11.1.
The processor is always free to invalidate additional entries in the TLBs and paging-
structure caches. The following are some examples:
• INVLPG may invalidate TLB entries for pages other than the one corresponding to
its linear-address operand.
• MOV to CR3 may invalidate TLB entries for global pages.
• On a processor supporting Hyper-Threading Technology, invalidations performed
on one logical processor may invalidate entries in the TLBs and paging-structure
caches used by other logical processors.
(Other instructions and operations may invalidate entries in the TLBs and the paging-
structure caches, but the instructions identified above are recommended.)
1. Even if the paging structures map the linear address using a page larger than 4 KBytes and there
are multiple TLB entries for that page (see Section 4.10.1), the instruction invalidates all of them.