Filter
Top Products
Vol. 3 5-47
PROTECTION
5.13.4 Exception Handling
When execute disable bit capability is enabled (IA32_EFER.NXE = 1), conditions for
a page fault to occur include the same conditions that apply to an Intel 64 or IA-32
processor without execute disable bit capability plus the following new condition: an
instruction fetch to a linear address that translates to physical address in a memory
page that has the execute-disable bit set.
An Execute Disable Bit page fault can occur at all privilege levels. It can occur on any
instruction fetch, including (but not limited to): near branches, far branches,
CALL/RET/INT/IRET execution, sequential instruction fetches, and task switches. The
execute-disable bit in the page translation mechanism is checked only when:
• IA32_EFER.NXE = 1.
• The instruction translation look-aside buffer (ITLB) is loaded with a page that is
not already present in the ITLB.
Table 5-9. Reserved Bit Checking WIth Execute-Disable Bit Capability Not Enabled
Mode Paging Mode Check Bits
32-bit KByte paging (non-PAE) No reserved bits checked
PSE36 - PDE, 4-MByte page Bit [21]
PSE36 - PDE, 4-KByte page No reserved bits checked
PSE36 - PTE No reserved bits checked
PAE - PDP table entry Bits [63:MAXPHYADDR] & [8:5] & [2:1]*
PAE - PDE, 2-MByte page Bits [63:MAXPHYADDR] & [20:13]*
PAE - PDE, 4-KByte page Bits [63:MAXPHYADDR]*
PAE - PTE Bits [63:MAXPHYADDR]*
64-bit PML4E Bit [63], bits [51:MAXPHYADDR]*
PDPTE Bit [63], bits [51:MAXPHYADDR]*
PDE, 2-MByte page Bit [63], bits [51:MAXPHYADDR] & [20:13]*
PDE, 4-KByte page Bit [63], bits [51:MAXPHYADDR]*
PTE Bit [63], bits [51:MAXPHYADDR]*
NOTES:
* MAXPHYADDR is the maximum physical address size and is indicated by
CPUID.80000008H:EAX[bits 7-0].