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Vol. 3 8-43
MULTIPLE-PROCESSOR MANAGEMENT
8.7.11 MICROCODE UPDATE Resources
In an Intel processor supporting Intel Hyper-Threading Technology, the microcode
update facilities are shared between the logical processors; either logical processor
can initiate an update. Each logical processor has its own BIOS signature MSR
(IA32_BIOS_SIGN_ID at MSR address 8BH). When a logical processor performs an
update for the physical processor, the IA32_BIOS_SIGN_ID MSRs for resident logical
processors are updated with identical information. If logical processors initiate an
update simultaneously, the processor core provides the necessary synchronization
needed to insure that only one update is performed at a time.
Operating system microcode update drivers that adhere to Intel’s guidelines do not
need to be modified to run on processors supporting Intel Hyper-Threading Tech-
nology.
8.7.12 Self Modifying Code
Intel processors supporting Intel Hyper-Threading Technology support self-modifying
code, where data writes modify instructions cached or currently in flight. They also
support cross-modifying code, where on an MP system writes generated by one
processor modify instructions cached or currently in flight on another. See
Section
8.1.3, “Handling Self- and Cross-Modifying Code,” for a description of the require-
ments for self- and cross-modifying code in an IA-32 processor.
8.7.13 Implementation-Specific Intel HT Technology Facilities
The following non-architectural facilities are implementation-specific in IA-32 proces-
sors supporting Intel Hyper-Threading Technology:
• Caches
• Translation lookaside buffers (TLBs)
• Thermal monitoring facilities
The Intel Xeon processor MP implementation is described in the following sections.
8.7.13.1 Processor Caches
For processors supporting Intel Hyper-Threading Technology, the caches are shared.
Any cache manipulation instruction that is executed on one logical processor has a
global effect on the cache hierarchy of the physical processor. Note the following:
• WBINVD instruction — The entire cache hierarchy is invalidated after modified
data is written back to memory. All logical processors are stopped from executing
until after the write-back and invalidate operation is completed. A special bus
cycle is sent to all caching agents. The amount of time or cycles for WBINVD to
complete will vary due to the size of different cache hierarchies and other factors.