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Vol. 3 16-43
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
16.9 LAST BRANCH, INTERRUPT, AND EXCEPTION
RECORDING (PENTIUM M PROCESSORS)
Like the Pentium 4 and Intel Xeon processor family, Pentium M processors provide
last branch interrupt and exception recording. The capability operates almost identi-
cally to that found in Pentium 4 and Intel Xeon processors. There are differences in
the shape of the stack and in some MSR names and locations. Note the following:
• MSR_DEBUGCTLB MSR — Enables debug trace interrupt, debug trace store,
trace messages enable, performance monitoring breakpoint flags, single
stepping on branches, and last branch. For Pentium M processors, this MSR is
located at register address 01D9H. See Figure 16-16 and the entries below for a
description of the flags.
— LBR (last branch/interrupt/exception) flag (bit 0) — When set, the
processor records a running trace of the most recent branches, interrupts,
and/or exceptions taken by the processor (prior to a debug exception being
generated) in the last branch record (LBR) stack. For more information, see
the “Last Branch Record (LBR) Stack” bullet below.
— BTF (single-step on branches) flag (bit 1) — When set, the processor
treats the TF flag in the EFLAGS register as a “single-step on branches” flag
rather than a “single-step on instructions” flag. This mechanism allows
single-stepping the processor on taken branches, interrupts, and exceptions.
See Section 16.4.3, “Single-Stepping on Branches, Exceptions, and Inter-
rupts,” for more information about the BTF flag.
— PBi (performance monitoring/breakpoint pins) flags (bits 5-2) —
When these flags are set, the performance monitoring/breakpoint pins on the
processor (BP0#, BP1#, BP2#, and BP3#) report breakpoint matches in the
corresponding breakpoint-address registers (DR0 through DR3). The
processor asserts then deasserts the corresponding BPi# pin when a
breakpoint match occurs. When a PBi flag is clear, the performance
monitoring/breakpoint pins report performance events. Processor execution
is not affected by reporting performance events.
Figure 16-15. LBR Branch Record Layout for the Intel Core Solo
and Intel
Core Duo Processor
0
63
From Linear Address
To Linear Address
32 - 31
MSR_LASTBRANCH_0 through MSR_LASTBRANCH_7