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10-8 Vol. 3
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Table 10-1 shows how the APIC registers are mapped into the 4-KByte APIC register
space. Registers are 32 bits, 64 bits, or 256 bits in width; all are aligned on 128-bit
boundaries. All 32-bit registers should be accessed using 128-bit aligned 32-bit loads
or stores. Some processors may support loads and stores of less than 32 bits to some
of the APIC registers. This is model specific behavior and is not guaranteed to work
on all processors. Any FP/MMX/SSE access to an APIC register, or any access that
touches bytes 4 through 15 of an APIC register may cause undefined behavior and
must not be executed. This undefined behavior could include hangs, incorrect results
or unexpected exceptions, including machine checks, and may vary between imple
-
mentations. Wider registers (64-bit or 256-bit) must be accessed using multiple 32-
bit loads or stores, with all accesses being 128-bit aligned.
The local APIC registers listed in Table 10-1 are not MSRs. The only MSR associated
with the programming of the local APIC is the IA32_APIC_BASE MSR (see Section
10.4.3, “Enabling or Disabling the Local APIC”).
NOTE
In processors based on Intel Microarchitecture (Nehalem) the Local
APIC ID Register is no longer Read/Write; it is Read Only.
Table 10-1 Local APIC Register Address Map
Address Register Name Software
Read/Write
FEE0 0000H Reserved
FEE0 0010H Reserved
FEE0 0020H Local APIC ID Register Read/Write.
FEE0 0030H Local APIC Version Register Read Only.
FEE0 0040H Reserved
FEE0 0050H Reserved
FEE0 0060H Reserved
FEE0 0070H Reserved
FEE0 0080H Task Priority Register (TPR) Read/Write.
FEE0 0090H Arbitration Priority Register
1
(APR) Read Only.
FEE0 00A0H Processor Priority Register (PPR) Read Only.
FEE0 00B0H EOI Register Write Only.
FEE0 00C0H Remote Read Register
1
(RRD) Read Only
FEE0 00D0H Logical Destination Register Read/Write.
FEE0 00E0H Destination Format Register Bits 0-27 Read only;
bits 28-31
Read/Write.