Filter
Top Products
Vol. 3 10-13
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
this, operating system software should avoid writing to the local APIC ID register. The
value returned by bits 31-24 of the EBX register (when the CPUID instruction is
executed with a source operand value of 1 in the EAX register) is always the Initial
APIC ID (determined by the platform initialization). This is true even if software has
changed the value in the Local APIC ID register.
The processor receives the hardware assigned APIC ID (or Initial APIC ID) by
sampling pins A11# and A12# and pins BR0# through BR3# (for the Pentium 4, Intel
Xeon, and P6 family processors) and pins BE0# through BE3# (for the Pentium
processor). The APIC ID latched from these pins is stored in the APIC ID field of the
local APIC ID register (see
Figure 10-6), and is used as the Initial APIC ID for the
processor.
For the P6 family and Pentium processors, the local APIC ID field in the local APIC ID
register is 4 bits. Encodings 0H through EH can be used to uniquely identify 15
different processors connected to the APIC bus. For the Pentium 4 and Intel Xeon
processors, the xAPIC specification extends the local APIC ID field to 8 bits. These
can be used to identify up to 255 processors in the system.
10.4.7 Local APIC State
The following sections describe the state of the local APIC and its registers following
a power-up or RESET, after the local APIC has been software disabled, following an
INIT reset, and following an INIT-deassert message.
Figure 10-6. Local APIC ID Register
31 27 24 0
ReservedAPIC ID
Address: 0FEE0 0020H
Value after reset: 0000 0000H
P6 family and Pentium processors
Pentium 4 processors, Xeon processors, and later processors
31 24 0
ReservedAPIC ID
MSR Address: 802H
31 0
x2APIC ID
x2APIC Mode