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11-36 Vol. 3
MEMORY CACHE CONTROL
— The width of the PhysMask field depends on the maximum physical address
size supported by the processor.
CPUID.80000008H reports the maximum physical address size supported by
the processor. If CPUID.80000008H is not available, software may assume
that the processor supports a 36-bit physical address size (then PhysMask is
24 bits wide and the upper 28 bits of IA32_MTRR_PHYSMASKn are reserved).
See the Note below.
• V (valid) flag, bit 11 — Enables the register pair when set; disables register
pair when clear.
All other bits in the IA32_MTRR_PHYSBASEn and IA32_MTRR_PHYSMASKn registers
are reserved; the processor generates a general-protection exception (#GP) if soft-
ware attempts to write to them.
Some mask values can result in ranges that are not continuous. In such ranges, the
area not mapped by the mask value is set to the default memory type. Intel does not
encourage the use of “discontinuous” ranges because they could require physical
memory to be present throughout the entire 4-GByte physical memory map. If
memory is not provided, the behaviour is undefined.
Figure 11-7. IA32_MTRR_PHYSBASEn and IA32_MTRR_PHYSMASKn Variable-Range
Register Pair
V — Valid
PhysMask — Sets range mask
IA32_MTRR_PHYSMASKn Register
63
0
Reserved
101112
V
Reserved
MAXPHYADDR
PhysMask
Type — Memory type for range
PhysBase — Base address of range
IA32_MTRR_PHYSBASEn Register
63
0
Reserved
1112
Type
MAXPHYADDR
PhysBase
78
Reserved
MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the maximum
physical address range supported by the processor. It is reported by CPUID leaf
function 80000008H. If CPUID does not support leaf 80000008H, the processor
supports 36-bit physical address size, then bit PhysMask consists of bits 35:12, and
bits 63:36 are reserved.