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Vol. 3 5-5
PROTECTION
The following sections describe how the processor uses these fields and flags to
perform the various categories of checks described in the introduction to this chapter.
5.2.1 Code Segment Descriptor in 64-bit Mode
Code segments continue to exist in 64-bit mode even though, for address calcula-
tions, the segment base is treated as zero. Some code-segment (CS) descriptor
content (the base address and limit fields) is ignored; the remaining fields function
normally (except for the readable bit in the type field).
Code segment descriptors and selectors are needed in IA-32e mode to establish the
processor’s operating mode and execution privilege-level. The usage is as follows:
• IA-32e mode uses a previously unused bit in the CS descriptor. Bit 53 is defined
as the 64-bit (L) flag and is used to select between 64-bit mode and compatibility
mode when IA-32e mode is active (IA32_EFER.LMA = 1). See
Figure 5-2.
— If CS.L = 0 and IA-32e mode is active, the processor is running in compati-
bility mode. In this case, CS.D selects the default size for data and addresses.
If CS.D = 0, the default data and address size is 16 bits. If CS.D = 1, the
default data and address size is 32 bits.
— If CS.L = 1 and IA-32e mode is active, the only valid setting is CS.D = 0. This
setting indicates a default operand size of 32 bits and a default address size
of 64 bits. The CS.L = 1 and CS.D = 1 bit combination is reserved for future
use and a #GP fault will be generated on an attempt to use a code segment
with these bits set in IA-32e mode.
• In IA-32e mode, the CS descriptor’s DPL is used for execution privilege checks
(as in legacy 32-bit mode).