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Vol. 3 19-35
ARCHITECTURE COMPATIBILITY
data cache and L2 cache of the P6 family processors. In the Intel486 processor,
setting these flags to (00B) enables write-through for the cache.
External system hardware can force the Pentium processor to disable caching or to
use the write-through cache policy should that be required. In the P6 family proces-
sors, the MTRRs can be used to override the CD and NW flags (see Table 11-6).
The P6 family and Pentium processors support page-level cache management in the
same manner as the Intel486 processor by using the PCD and PWT flags in control
register CR3, the page-directory entries, and the page-table entries. The Intel486
processor, however, is not affected by the state of the PWT flag since the internal
cache of the Intel486 processor is a write-through cache.
19.29.1 Self-Modifying Code with Cache Enabled
On the Intel486 processor, a write to an instruction in the cache will modify it in both
the cache and memory. If the instruction was prefetched before the write, however,
the old version of the instruction could be the one executed. To prevent this problem,
it is necessary to flush the instruction prefetch unit of the Intel486 processor by
coding a jump instruction immediately after any write that modifies an instruction.
The P6 family and Pentium processors, however, check whether a write may modify
an instruction that has been prefetched for execution. This check is based on the
linear address of the instruction. If the linear address of an instruction is found to be
present in the prefetch queue, the P6 family and Pentium processors flush the
prefetch queue, eliminating the need to code a jump instruction after any writes that
modify an instruction.
Because the linear address of the write is checked against the linear address of the
instructions that have been prefetched, special care must be taken for self-modifying
code to work correctly when the physical addresses of the instruction and the written
data are the same, but the linear addresses differ. In such cases, it is necessary to
execute a serializing operation to flush the prefetch queue after the write and before
executing the modified instruction. See
Section 8.3, “Serializing Instructions,” for
more information on serializing instructions.
NOTE
The check on linear addresses described above is not in practice a
concern for compatibility. Applications that include self-modifying
code use the same linear address for modifying and fetching the
instruction. System software, such as a debugger, that might
possibly modify an instruction using a different linear address than
that used to fetch the instruction must execute a serializing
operation, such as IRET, before the modified instruction is executed.