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Vol. 3 4-35
PAGING
is 1; it is 0 if a user-mode (CPL = 3) access did so. This flag describes the access
causing the page-fault exception, not the access rights specified by paging.
• RSVD flag (bit 3).
This flag is 1 if there is no valid translation for the linear address because a
reserved bit was set in one of the paging-structure entries used to translate that
address. (Because reserved bits are not checked in a paging-structure entry
whose P flag is 0, bit 3 of the error code can be set only if bit 0 is also set.)
Bits reserved in the paging-structure entries are reserved for future functionality.
Software developers should be aware that such bits may be used in the future
and that a paging-structure entry that causes a page-fault exception on one
processor might not do so in the future.
• I/D flag (bit 4).
Use of this flag depends on the settings of CR4.PAE and IA32_EFER.NXE:
— CR4.PAE = 0 (32-bit paging is in use) or IA32_EFER.NXE= 0.
This flag is 0.
— CR4.PAE = 1 (either PAE paging or IA-32e paging is in use) and
IA32_EFER.NXE= 1.
If the access causing the page-fault exception was an instruction fetch, this
flag is 1; otherwise, it is 0. This flag describes the access causing the page-
fault exception, not the access rights specified by paging.
Figure 4-11. Page-Fault Error Code
The fault was caused by a non-present page.
The fault was caused by a page-level protection violation.
The access causing the fault was a read.
The access causing the fault was a write.
The access causing the fault originated when the processor
was executing in supervisor mode.
The access causing the fault originated when the processor
was executing in user mode.
31
0
Reserved
123
4
The fault was not caused by reserved bit violation.
The fault was caused by a reserved bit set to 1 in some
P
0
1
W/R
0
1
U/S
0
RSVD
0
1
1
I/D
I/D
0
The fault was not caused by an instruction fetch.
1
The fault was caused by an instruction fetch.
P
W/R
U/S
RSVD
paging-structure entry.