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13-6 Vol. 3
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR
to a 16-byte boundary will also generate a general-protection exception,
instead a stack-segment fault exception (#SS).
— Page fault (#PF).
— Alignment check (#AC). When enabled, this type of alignment check
operates on operands that are less than 128-bits in size: 16-bit, 32-bit, and
64-bit. To enable the generation of alignment check exceptions, do the
following:
• Set the AM flag (bit 18 of control register CR0)
• Set the AC flag (bit 18 of the EFLAGS register)
• CPL must be 3
If alignment check exceptions are enabled, 16-bit, 32-bit, and 64-bit
misalignment will be detected for the MOVUPD and MOVUPS instructions;
detection of 128-bit misalignment is not guaranteed and may vary with
implementation.
• System Exceptions:
— Invalid-opcode exception (#UD). This exception is generated when executing
SSE/SSE2/SSE3/SSSE3 instructions under the following conditions:
• SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 feature flags returned by
CPUID are set to 0. This condition does not affect the CLFLUSH
instruction, nor POPCNT.
• The CLFSH feature flag returned by the CPUID instruction is set to 0. This
exception condition only pertains to the execution of the CLFLUSH
instruction.
• The POPCNT feature flag returned by the CPUID instruction is set to 0.
This exception condition only pertains to the execution of the POPCNT
instruction.
• The EM flag (bit 2) in control register CR0 is set to 1, regardless of the
value of TS flag (bit 3) of CR0. This condition does not affect the PAUSE,
PREFETCHh, MOVNTI, SFENCE, LFENCE, MFENSE, CLFLUSH, CRC32 and
POPCNT instructions.
• The OSFXSR flag (bit 9) in control register CR4 is set to 0. This condition
does not affect the PAVGB, PAVGW, PEXTRW, PINSRW, PMAXSW, PMAXUB,
PMINSW, PMINUB, PMOVMSKB, PMULHUW, PSADBW, PSHUFW,
MASKMOVQ, MOVNTQ, MOVNTI, PAUSE, PREFETCHh, SFENCE, LFENCE,
MFENCE, CLFLUSH, CRC32 and POPCNT instructions.
• Executing a instruction that causes a SIMD floating-point exception when
the OSXMMEXCPT flag (bit 10) in control register CR4 is set to 0. See
Section 13.5.1, “Using the TS Flag to Control the Saving of the x87 FPU,
MMX, SSE, SSE2, SSE3 SSSE3 and SSE4 State.”