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Vol. 3 11-37
MEMORY CACHE CONTROL
NOTE
It is possible for software to parse the memory descriptions that
BIOS provides by using the ACPI/INT15 e820 interface mechanism.
This information then can be used to determine how MTRRs are
initialized (for example: allowing the BIOS to define valid memory
ranges and the maximum memory range supported by the platform,
including the processor).
See Section 11.11.4.1, “MTRR Precedences,” for information on overlapping variable
MTRR ranges.
11.11.2.4 System-Management Range Register Interface
If IA32_MTRRCAP[bit 11] is set, the processor supports the SMRR interface to
restrict access to a specified memory address range used by system-management
mode (SMM) software (see Section 26.4.2.1). If the SMRR interface is supported,
SMM software is strongly encouraged to use it to protect the SMI code and data
stored by SMI handler in the SMRAM region.
The system-management range registers consist of a pair of MSRs (see Figure 11-8).
The IA32_SMRR_PHYSBASE MSR defines the base address for the SMRAM memory
range and the memory type used to access it in SMM. The IA32_SMRR_PHYSMASK
MSR contains a valid bit and a mask that determines the SMRAM address range
protected by the SMRR interface. These MSRs may be written only in SMM; an
attempt to write them outside of SMM causes a general-protection exception.
1
Figure 11-8 shows flags and fields in these registers. The functions of these flags and
fields are the following:
• Type field, bits 0 through 7 — Specifies the memory type for the range (see
Table 11-8 for the encoding of this field).
• PhysBase field, bits 12 through 31 — Specifies the base address of the
address range. The address must be less than 4 GBytes and is automatically
aligned on a 4-KByte boundary.
• PhysMask field, bits 12 through 31 — Specifies a mask that determines the
range of the region being mapped, according to the following relationships:
— Address_Within_Range AND PhysMask = PhysBase AND PhysMask
— This value is extended by 12 bits at the low end to form the mask value. For
more information: see
Section 11.11.3, “Example Base and Mask Calcula-
tions.”
• V (valid) flag, bit 11 — Enables the register pair when set; disables register
pair when clear.
1. For some processor models, these MSRs can be accessed by RDMSR and WRMSR only if the
SMRR interface has been enabled in the IA32_FEATURE_CONTROL MSR. See Appendix B.