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13-4 Vol. 3
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR
• OSFXSR and OSXMMEXCPT flags in control register CR4
• SSE/SSE2/SSE3/SSSE3/SSE4 feature flags returned by CPUID
• EM, MP, and TS flags in control register CR0
Table 13-1. Action Taken for Combinations of OSFXSR, OSXMMEXCPT, SSE, SSE2,
SSE3, EM, MP, and TS
1
CR4 CPUID CR0 Flags
OSFXSR OSXMMEXCPT SSE,
SSE2,
SSE3
2
SSE4_1
3
EM MP
4
TS Action
0 X
5
X X 1 X #UD exception.
1 X 0 X 1 X #UD exception.
1 X 1 1 1 X #UD exception.
1 0 1 0 1 0 Execute instruction; #UD exception
if unmasked SIMD floating-point
exception is detected.
1 1 1 0 1 0 Execute instruction; #XM exception
if unmasked SIMD floating-point
exception is detected.
1 X 1 0 1 1 #NM exception.
NOTES:
1. For execution of any SSE/SSE2/SSE3 instruction except the PAUSE, PREFETCHh, SFENCE,
LFENCE, MFENCE, MOVNTI, and CLFLUSH instructions.
2. Exception conditions due to CR4.OSFXSR or CR4.OSXMMEXCPT do not apply to FISTTP.
3. Only applies to DPPS, DPPD, ROUNDPS, ROUNDPD, ROUNDSS, ROUNDSD.
4. For processors that support the MMX instructions, the MP flag should be set.
5. X — Don’t care.