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Vol. 3 15-33
MACHINE-CHECK ARCHITECTURE
caused the error. Eviction and snoop requests apply only to the caches. All of
the other requests apply to TLBs, caches and interconnects.
15.9.2.5 Bus and Interconnect Errors
The bus and interconnect errors are defined with the 2-bit PP (participation),
1-bit T (time-out), and 2-bit II (memory or I/O) sub-fields, in addition to the
LL and RRRR sub-fields (see
Table 15-13). The bus error conditions are
implementation dependent and related to the type of bus implemented by
the processor. Likewise, the interconnect error conditions are predicated on
a specific implementation-dependent interconnect model that describes the
connections between the different levels of the storage hierarchy. The type
of bus is implementation dependent, and as such is not specified in this
document. A bus or interconnect transaction consists of a request involving
an address and a response.
Table 15-12. Encoding of Request (RRRR) Sub-Field
Request Type Mnemonic Binary Encoding
Generic Error ERR 0000
Generic Read RD 0001
Generic Write WR 0010
Data Read DRD 0011
Data Write DWR 0100
Instruction Fetch IRD 0101
Prefetch PREFETCH 0110
Eviction EVICT 0111
Snoop SNOOP 1000
Table 15-13. Encodings of PP, T, and II Sub-Fields
Sub-Field Transaction Mnemonic Binary Encoding
PP (Participation) Local processor* originated request SRC 00
Local processor* responded to request RES 01
Local processor* observed error as
third party
OBS 10
Generic 11
T (Time-out) Request timed out TIMEOUT 1
Request did not time out NOTIMEOUT 0
II (Memory or I/O) Memory Access M 00
Reserved 01