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10-52 Vol. 3
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Here, the TPR value is the task priority value in the TPR (see Figure 10-26), the IRRV
value is the vector number for the highest priority bit that is set in the IRR (see
Figure 10-28) or 00H (if no IRR bit is set), and the ISRV value is the vector number
for the highest priority bit that is set in the ISR (see Figure 10-28). Following arbitra-
tion among the destination processors, the processor with the lowest value in its APR
handles the IPI and the other processors ignore it.
(P6 family and Pentium processors.) For these processors, if a focus processor
exists, it may accept the interrupt, regardless of its priority. A processor is said to be
the focus of an interrupt if it is currently servicing that interrupt or if it has a pending
request for that interrupt. For Intel Xeon processors, the concept of a focus processor
is not supported.
In operating systems that use the lowest priority delivery mode but do not update
the TPR, the TPR information saved in the chipset will potentially cause the interrupt
to be always delivered to the same processor from the logical set. This behavior is
functionally backward compatible with the P6 family processor but may result in
unexpected performance implications.
10.7.3 IPI Delivery and Acceptance
When the low double-word of the ICR is written to, the local APIC creates an IPI
message from the information contained in the ICR and sends the message out on
the system bus (Pentium 4 and Intel Xeon processors) or the APIC bus (P6 family and
Pentium processors). The manner in which these IPIs are handled after being issues
in described in
Section 10.9, “Handling Interrupts.”
10.7.4 SELF IPI Register
SELF IPIs are used extensively by some system software. The x2APIC architecture
introduces a new register interface. This new register is dedicated to the purpose of
sending self-IPIs with the intent of enabling a highly optimized path for sending self-
IPIs.
Figure 10-23 provides the layout of the SELF IPI register. System software only spec-
ifies the vector associated with the interrupt to be sent. The semantics of sending a
self-IPI via the SELF IPI register are identical to sending a self targeted edge trig
-
gered fixed interrupt with the specified vector. Specifically the semantics are identical
to the following settings for an inter-processor interrupt sent via the ICR - Destina
-
tion Shorthand (ICR[19:18] = 01 (Self)), Trigger Mode (ICR[15] = 0 (Edge)),
Delivery Mode (ICR[10:8] = 000 (Fixed)), Vector (ICR[7:0] = Vector).