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7-4 Vol. 3
TASK MANAGEMENT
page tables as other privilege-level-3 tasks can access code and corrupt data and the
stack of other tasks.
Use of task management facilities for handling multitasking applications is optional.
Multitasking can be handled in software, with each software defined task executed in
the context of a single IA-32 architecture task.
7.2 TAS K MANAGE MENT DATA STRUCTURES
The processor defines five data structures for handling task-related activities:
• Task-state segment (TSS).
• Task-gate descriptor.
• TSS descriptor.
• Task register.
• NT flag in the EFLAGS register.
When operating in protected mode, a TSS and TSS descriptor must be created for at
least one task, and the segment selector for the TSS must be loaded into the task
register (using the LTR instruction).
7.2.1 Task-State Segment (TSS)
The processor state information needed to restore a task is saved in a system
segment called the task-state segment (TSS). Figure 7-2 shows the format of a TSS
for tasks designed for 32-bit CPUs. The fields of a TSS are divided into two main cate-
gories: dynamic fields and static fields.
For information about 16-bit Intel 286 processor task structures, see Section 7.6,
“16-Bit Task-State Segment (TSS).” For information about 64-bit mode task struc-
tures, see Section 7.7, “Task Management in 64-bit Mode.”