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4-12 Vol. 3
PAGING
— Bits 31:12 are from the PTE.
Table 4-4. Format of a 32-Bit Page-Directory Entry that Maps a 4-MByte Page
Bit
Position(s)
Contents
0 (P) Present; must be 1 to map a 4-MByte page
1 (R/W) Read/write; if 0, writes may not be allowed to the 4-MByte page referenced by
this entry (depends on CPL and CR0.WP; see Section 4.6)
2 (U/S) User/supervisor; if 0, accesses with CPL=3 are not allowed to the 4-MByte page
referenced by this entry (see Section 4.6)
3 (PWT) Page-level write-through; indirectly determines the memory type used to access
the 4-MByte page referenced by this entry (see Section 4.9)
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access
the 4-MByte page referenced by this entry (see Section 4.9)
5 (A) Accessed; indicates whether software has accessed the 4-MByte page referenced
by this entry (see Section 4.8)
6 (D) Dirty; indicates whether software has written to the 4-MByte page referenced by
this entry (see Section 4.8)
7 (PS) Page size; must be 1 (otherwise, this entry references a page table; see Table 4-5)
8 (G) Global; if CR4.PGE = 1, determines whether the translation is global (see Section
4.10); ignored otherwise
11:9 Ignored
12 (PAT) If the PAT is supported, indirectly determines the memory type used to access the
4-MByte page referenced by this entry (see Section 4.9); otherwise, reserved
(must be 0)
1
M–20:13 Bits M–1:32 of physical address of the 4-MByte page referenced by this entry
2
21:M–19 Reserved (must be 0)
31:22 Bits 31:22 of physical address of the 4-MByte page referenced by this entry
NOTES:
1. See Section 4.1.4 for how to determine whether the PAT is supported.
2. If the PSE-36 mechanism is not supported, M is 32, and this row does not apply. If the PSE-36
mechanism is supported, M is the minimum of 40 and MAXPHYADDR (this row does not apply if
MAXPHYADDR = 32). See Section 4.1.4 for how to determine MAXPHYADDR and whether the
PSE-36 mechanism is supported.