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Vol. 3 4-43
PAGING
— The processor may create a PDPTE-cache entry even if there are no transla-
tions for any linear address that might use that entry.
— If the processor creates a PDPTE-cache entry, the processor may retain it
unmodified even if software subsequently modifies the corresponding PML4E
or PDPTE in memory.
• PDE cache. The use of the PDE cache depends on the paging mode:
— For 32-bit paging, each PDE-cache entry is referenced by a 10-bit value and
is used for linear addresses for which bits 31:22 have that value.
— For PAE paging, each PDE-cache entry is referenced by an 11-bit value and is
used for linear addresses for which bits 31:21 have that value.
— For IA-32e paging, each PDE-cache entry is referenced by a 27-bit value and
is used for linear addresses for which bits 47:21 have that value.
A PDE-cache entry contains information from the PML4E, PDPTE, and PDE used to
translate the relevant linear addresses (for 32-bit paging and PAE paging, only
the PDE applies):
— The physical address from the PDE (the address of the page table). (No PDE-
cache entry is created for a PDE that maps a page.)
— The logical-AND of the R/W flags in the PML4E, PDPTE, and PDE.
— The logical-AND of the U/S flags in the PML4E, PDPTE, and PDE.
— The logical-OR of the XD flags in the PML4E, PDPTE, and PDE.
— The values of the PCD and PWT flags of the PDE.
The following items detail how a processor may use the PDE cache (references
below to PML4Es and PDPTEs apply on to IA-32e paging):
— If the processor has a PDE-cache entry for a linear address, it may use that
entry when translating the linear address (instead of the PML4E, the PDPTE,
and the PDE in memory).
— The processor does not create a PDE-cache entry unless the P flag is 1, the PS
flag is 0, and the reserved bits are 0 in the PML4E, the PDPTE, and the PDE in
memory.
— The processor does not create a PDE-cache entry unless the accessed flag is
1 in the PML4E, the PDPTE, and the PDE in memory; before caching a trans-
lation, the processor sets any accessed flags that are not already 1.
— The processor may create a PDE-cache entry even if there are no translations
for any linear address that might use that entry.
— If the processor creates a PDE-cache entry, the processor may retain it
unmodified even if software subsequently modifies the corresponding PML4E,
the PDPTE, or the PDE in memory.
Information from a paging-structure entry can be included in entries in the paging-
structure caches for other paging-structure entries referenced by the original entry.