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Vol. 3 11-21
MEMORY CACHE CONTROL
When normal caching is in effect, the effective memory type shown in Table 11-6 is
determined using the following rules:
1. If the PCD and PWT attributes for the page are both 0, then the effective
memory type is identical to the MTRR-defined memory type.
2. If the PCD flag is set, then the effective memory type is UC.
3. If the PCD flag is clear and the PWT flag is set, the effective memory type is WT
for the WB memory type and the MTRR-defined memory type for all other
memory types.
4. Setting the PCD and PWT flags to opposite values is considered model-specific for
the WP and WC memory types and architecturally-defined for the WB, WT, and
UC memory types.
Table 11-6. Effective Page-Level Memory Type for Pentium Pro and
Pentium II Processors
MTRR Memory Type
1
PCD Value PWT Value Effective Memory Type
UC X X UC
WC 0 0 WC
0 1 WC
1 0 WC
1 1 UC
WT 0 X WT
1 X UC
WP 0 0 WP
0 1 WP
1 0 WC
1 1 UC
WB 0 0 WB
0 1 WT
1 X UC
NOTE:
1. These effective memory types also apply to the Pentium 4, Intel Xeon, and Pentium III proces-
sors when the PAT bit is not used (set to 0) in page-table and page-directory entries.