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Vol. 3 14-15
POWER AND THERMAL MANAGEMENT
After the second temperature sensor has been tripped, the thermal monitor
(TM1/TM2) will remain engaged for a minimum time period (on the order of 1 ms).
The thermal monitor will remain engaged until the processor core temperature drops
below the preset trip temperature of the temperature sensor, taking hysteresis into
account.
While the processor is in a stop-clock state, interrupts will be blocked from inter-
rupting the processor. This holding off of interrupts increases the interrupt latency,
but does not cause interrupts to be lost. Outstanding interrupts remain pending until
clock modulation is complete.
The thermal monitor can be programmed to generate an interrupt to the processor
when the thermal sensor is tripped. The delivery mode, mask and vector for this
interrupt can be programmed through the thermal entry in the local APIC’s LVT (see
Section 10.6.1, “Local Vector Table”). The low-temperature interrupt enable and
high-temperature interrupt enable flags in the IA32_THERM_INTERRUPT MSR (see
Figure 14-9) control when the interrupt is generated; that is, on a transition from a
temperature below the trip point to above and/or vice-versa.
• High-Temperature Interrupt Enable flag, bit 0 — Enables an interrupt to be
generated on the transition from a low-temperature to a high-temperature when
set; disables the interrupt when clear.(R/W).
• Low-Temperature Interrupt Enable flag, bit 1 — Enables an interrupt to be
generated on the transition from a high-temperature to a low-temperature when
set; disables the interrupt when clear.
The thermal monitor interrupt can be masked by the thermal LVT entry. After a
power-up or reset, the low-temperature interrupt enable and high-temperature
Figure 14-8. IA32_THERM_STATUS MSR
Figure 14-9. IA32_THERM_INTERRUPT MSR
63 0
Reserved
12
Thermal Status
Thermal Status Log
63 0
Reserved
12
High-Temperature Interrupt Enable
Low-Temperature Interrupt Enable