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Vol. 3 4-17
PAGING
Table 4-8 gives the format of a PDPTE. If any of the PDPTEs sets both the P flag
(bit 0) and any reserved bit, the MOV to CR instruction causes a general-protection
exception (#GP(0)) and the PDPTEs are not loaded.
1
As show in Table 4-8, bits 2:1,
8:5, and 63:MAXPHYADDR are reserved in the PDPTEs.
4.4.2 Linear-Address Translation with PAE Paging
PAE paging may map linear addresses to either 4-KByte pages or 2-MByte pages.
Figure 4-5 illustrates the translation process when it produces a 4-KByte page;
Figure 4-6 covers the case of a 2-MByte page. The following items describe the PAE
paging process in more detail as well has how the page size is determined:
• Bits 31:30 of the linear address select a PDPTE register (see Section 4.4.1); this
is PDPTEi, where i is the value of bits 31:30.
2
Because a PDPTE register is
identified using bits 31:30 of the linear address, it controls access to a 1-GByte
region of the linear-address space. If the P flag (bit 0) of PDPTEi is 0, the
Table 4-8. Format of an PAE Page-Directory-Pointer-Table Entry (PDPTE)
Bit
Position(s)
Contents
0 (P) Present; must be 1 to reference a page directory
2:1 Reserved (must be 0)
3 (PWT) Page-level write-through; indirectly determines the memory type used to access
the page directory referenced by this entry (see Section 4.9)
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access
the page directory referenced by this entry (see Section 4.9)
8:5 Reserved (must be 0)
11:9 Ignored
M–1:12 Physical address of 4-KByte aligned page directory referenced by this entry
1
NOTES:
1. M is an abbreviation for MAXPHYADDR, which is at most 52; see Section 4.1.4.
63:M Reserved (must be 0)
1. On some processors, reserved bits are checked even in PDPTEs in which the P flag (bit 0) is 0.
2. With PAE paging, the processor does not use CR3 when translating a linear address (as it does
the other paging modes). It does not access the PDPTEs in the page-directory-pointer table dur-
ing linear-address translation.