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Vol. 3 7-3
TASK MANAGEMENT
7.1.3 Executing a Task
Software or the processor can dispatch a task for execution in one of the following
ways:
• A explicit call to a task with the CALL instruction.
• A explicit jump to a task with the JMP instruction.
• An implicit call (by the processor) to an interrupt-handler task.
• An implicit call to an exception-handler task.
• A return (initiated with an IRET instruction) when the NT flag in the EFLAGS
register is set.
All of these methods for dispatching a task identify the task to be dispatched with a
segment selector that points to a task gate or the TSS for the task. When dispatching
a task with a CALL or JMP instruction, the selector in the instruction may select the
TSS directly or a task gate that holds the selector for the TSS. When dispatching a
task to handle an interrupt or exception, the IDT entry for the interrupt or exception
must contain a task gate that holds the selector for the interrupt- or exception-
handler TSS.
When a task is dispatched for execution, a task switch occurs between the currently
running task and the dispatched task. During a task switch, the execution environ-
ment of the currently executing task (called the task’s state or context) is saved in
its TSS and execution of the task is suspended. The context for the dispatched task is
then loaded into the processor and execution of that task begins with the instruction
pointed to by the newly loaded EIP register. If the task has not been run since the
system was last initialized, the EIP will point to the first instruction of the task’s code;
otherwise, it will point to the next instruction after the last instruction that the task
executed when it was last active.
If the currently executing task (the calling task) called the task being dispatched (the
called task), the TSS segment selector for the calling task is stored in the TSS of the
called task to provide a link back to the calling task.
For all IA-32 processors, tasks are not recursive. A task cannot call or jump to itself.
Interrupts and exceptions can be handled with a task switch to a handler task. Here,
the processor performs a task switch to handle the interrupt or exception and auto
-
matically switches back to the interrupted task upon returning from the interrupt-
handler task or exception-handler task. This mechanism can also handle interrupts
that occur during interrupt tasks.
As part of a task switch, the processor can also switch to another LDT, allowing each
task to have a different logical-to-physical address mapping for LDT-based segments.
The page-directory base register (CR3) also is reloaded on a task switch, allowing
each task to have its own set of page tables. These protection facilities help isolate
tasks and prevent them from interfering with one another.
If protection mechanisms are not used, the processor provides no protection
between tasks. This is true even with operating systems that use multiple privilege
levels for protection. A task running at privilege level 3 that uses the same LDT and