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WORKING WITH THE CPU
MemoryManagement Unit (MMU)
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page tables have 1024 entries, splitting the 1 MB that the table describes into 1 KB
blocks. The next two sections show the format of a fine page table descriptor and
define the fine page table descriptor bit assignments.
Note:
If a fine page table descriptor is returned from the first-level fetch, a
second-level fetch is initiated.
Fine page table
descriptor format
Fine page table
descriptor bit
description
Translating
section references
This figure illustrates the complete section translation sequence.
Fine page table base address
SBZ
Domain 1 1 1
10234589111231
SBZ
Bits Description
[31:12] Forms the base for referencing the second-level descriptor (the fine page table index for
the entry is derived from the MVA).
[11:9] Always written as 0.
[8:5] Specifies one of the 16 possible domains (held in the Domain Access Control register)
that contain primary access controls.
4 Always written as 1.
[3:2} Always written as 0.
[1:0] Must be 11 to indicate a fine page table descriptor.