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ETHERNET COMMUNICATION MODULE
Resets
274 Hardware Reference NS9215
Status bits The status bits for all interrupts are available in the Ethernet Interrupt Status
register, and the associated enables are available in the Ethernet Interrupt Enable
register. Each interrupt status bit is cleared by writing a 1 to it.
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Resets
This table provides a summary of all resets used for the Ethernet front-end and
MAC, as well as the modules the resets control.
No receive buffers No buffer is available for this frame because all 4 buffer rings are
disabled, full, or no available buffer is big enough for the frame.
RX
Receive buffers full No buffer is available for this frame because all 4 buffers are
disabled or full.
RX
RX buffer ready Frame available in
RX_FIFO. (Used for diagnostics.) RX
Statistics counter
overflow
One of the statistics counters has overflowed. Individual
counters can be masked using the CAM1 and CAM2 registers.
TX
Transmit buffer closed I bit set in Transmit buffer descriptor and buffer closed. TX
Transmit buffer not ready F bit not set in transmit buffer descriptor when read from TX
buffer descriptor RAM, for a frame in progress.
TX
Transmit complete Frame transmission complete. TX
TXERR Frame not transmitted successfully. TX
TXIDLE
TX_WR logic in idle mode because there are no frames to send. TX
Interrupt condition Description Interrupt
Bit field Register Active
state
Default
state
Modules reset
ERX Ethernet General Control
Register #1
0 0 RX_RD, RX_WR
ETX Ethernet General Control
Register #1
0 0 TX_RD, TX_WR
MAC_HRST Ethernet General Control
Register #1
1 0 MAC, STAT, RX_WR, TX_RD,
programmable registers in Station
Address Logic
SRST MAC1 1 1 MAC (except programmable
registers), Station Address Logic
(except programmable registers),
RX_WR, TX_RD
RPERFUN MAC1 1 0 MAC RX logic
RPEMCST MAC1 1 0 MAC PEMCS (TX side)