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SYSTEM CONTROL MODULE
AHB Error Detect Status 2
160 Hardware Reference NS9215
The AHB Error Detect Status 1 register records the haddr[31:0] value present when any
AHB error is found. Note that this value is not reset on powerup but is reset when
the AHB Error Interrupt Clear bit is set in the AHB Error Monitoring Configuration
register (*).
Register
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Error Detect Status 2
Address: A090 001C
The AHB Error Detect Status 2 register records AHB master and slave values present
when any AHB error is found. This register also records which error condition was
triggered. Note that this value is not reset on powerup but is reset when the AHB
Interrupt Clear bit is set in the AHB Error Monitoring Configuration register (*).
Register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
EDSI
EDSI
Bits Access Mnemonic Reset Description
D31:00 * EDS1 Not reset The
haddr[31:0] value recorded during a slave error
response.
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
HPR
Reserved
HBRST
IE DE ER
Reser
ved
Re
ser
ved
HSZ
HMSTR
H
W
R