Digi NS9215 Computer Hardware User Manual


 
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WORKING WITH THE CPU
Noncachable instruction fetches
www.digiembedded.com 133
In this figure:
A = log
2
associativity
For example, with a 4-way cache A = 2:
S = log
2
NSETS
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Noncachable instruction fetches
The ARM926EJ-S processor performs speculative noncachable instruction fetches to
increase performance. Speculative instruction fetching is enabled at reset.
Note:
It is recommended that you use ICache rather than noncachable code, when
possible. Noncachable code previously has been used for operating system
boot loaders and for preventing cache pollution. ICache, however, can be
enabled without the MMU being enabled, and cache pollution can be
controlled using the cache lockdown register.
Self-modifying
code
A four-word buffer holds speculatively fetched instructions. Only sequential
instructions are fetched speculatively; if the ARM926EJ-S issues a nonsequential
instruction fetch, the contents of the buffer are discarded (flushed). In situations on
which the contents of the prefetch buffer might become invalid during a sequence
of sequential instruction fetches by the processor core (for example, turning the
MMU on or off, or turning on the ICache), the prefetch buffer also is flushed. This
avoids the necessity of performing an explicit Instruction Memory Barrier (IMB)
operation, except when self-modifying code is used. Because the prefetch buffer is
flushed when the ARM926EJ-S core issues a nonsequential instruction fetch, a
branch instruction (or equivalent) can be used to implement the required IMB
behavior, as shown in this code sequence:
LDMIA R0,{R1-R5} ; load code sequence into R1-R5
ADR R0,self_mod_code
STMIA R0,{R1-R5} ; store code sequence (nonbuffered region)
B self_mod_code ; branch to modified code
self_mod_code:
This IMB application applies only to the ARM926EJ-S processor running code from a
noncachable region of memory. If code is run from a cachable region of memory, or
a different device is used, a different IMB implementation is required. IMBs are
discussed in "Instruction Memory Barrier," beginning on page 134.