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WORKING WITH THE CPU
System control processor (CP15) registers
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Java instruction
set
In Java state, the processor core executes a majority of Java bytecodes naturally.
Bytecodes are decoded in two states, compared to a single decode stage when in
ARM/Thumb mode. See “Jazelle(Java)” on page 104 for more information about
Java.
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System control processor (CP15) registers
The system control processor (CP15) registers configure and control most of the
options in the ARM926EJ-S processor. Access the CP15 registers using only the MRC
and MCR instructions in a privileged mode; the instructions are provided in the
explanation of each applicable register. Using other instructions, or MRC and MCR in
unprivileged mode, results in an UNDEFINED instruction exception.
ARM926EJ-S
system addresses
The ARM926EJ-S has three distinct types of addresses:
In the ARM926EJ-S domain: Virtual address (VA)
In the Cache and MMU domain: Modified virtual address (MVA)
In the AMBA domain: Physical address (PA)
Address
manipulation
example
This is an example of the address manipulation that occurs when the ARM926EJ-S
core requests an instruction:
1 The ARM926EJ-S core issues the virtual address of the instruction.
2 The virtual address is translated using the FCSE PID (fast context switch
extension process ID) value to the modified virtual address. The instruction
cache (ICache) and memory management unit (MMU) find the modified virtual
address (see “R13:Process ID register” on page 102).
3 If the protection check carried out by the MMU on the modified virtual address
does not abort and the modified virtual address tag is in the ICache, the
instruction data is returned to the ARM926EJ-S core.
If the protection check carried out by the MMU on the modified virtual
address does not abort but the cache misses (the MVA tag is not in the
cache), the MMU translates the modified virtual address to produce the
physical address. This address is given to the AMBA bus interface to perform
an external access.
Accessing CP15
registers
Use only
MRC and MCR instructions, only in privileged mode, to access CP15
registers. Figure 1 shows the MRC and MCR instruction bit pattern.