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ETHERNET COMMUNICATION MODULE
TX Buffer Descriptor RAM
332 Hardware Reference NS9215
Register bit
assignment
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TX Buffer Descriptor RAM
Address: A060 1000
The TX buffer descriptor RAM holds 64 transmit buffer descriptors on-chip. Each
buffer descriptor occupies four locations in the RAM, and the RAM is implemented
as a 256x32 device. This is the format of the TX buffer descriptor RAM:
Offset+0
Bits Access Mnemonic Reset Description
D31:08 R Reserved N/A Read as 0
D07 R/W MFILTEN7 0x0000 0000 Enable entry 7 of multicast address filter
0 Disable entry
1 Enable entry
D06 R/W MFILTEN6 0x0000 0000 Enable entry 6 of multicast address filter
0 Disable entry
1 Enable entry
D05 R/W MFILTEN5 0x0000 0000 Enable entry 5 of multicast address filter
0 Disable entry
1 Enable entry
D04 R/W MFILTEN4 0x0000 0000 Enable entry 4 of multicast address filter
0 Disable entry
1 Enable entry
D03 R/W MFILTEN3 0x0000 0000 Enable entry 3 of multicast address filter
0 Disable entry
1 Enable entry
D02 R/W MFILTEN2 0x0000 0000 Enable entry 2 of multicast address filter
0 Disable entry
1 Enable entry
D01 R/W MFILTEN1 0x0000 0000 Enable entry 1 of multicast address filter
0 Disable entry
1 Enable entry
D00 R/W MFILTEN0 0x0000 0000 Enable entry 0 of multicast address filter
0 Disable entry
1 Enable entry
D31:00 R/W Source address