Filter
Top Products
. . . . .
TIMING
Memory Timing
www.digiembedded.com 495
static_rd_0wt.mif
Static RAM read
cycles with 0 wait
states
WTRD = 1
WOEN = 0
If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-
bit, and 8-bit read cycles.
If the PB field is set to 0, the byte_lane signal will always be high.
M24M23
M28M27
M20M19
M18M17
M26
M25
St ti RAM d l
clk_out
data<31:0>
addr<27:0>
st_cs_n<3:0>
oe_n
byte_lane<3:0>