Filter
Top Products
. . . . .
I/O HUB MODULE
[Module] Direct Mode RX Data FIFO
www.digiembedded.com 379
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
[ Module] Direct Mode RX Data FIFO
Addresses: 9000_0014 / 9000_8014 / 9001_0014 / 9001_8014 / 9002_0014 /
9002_8014 / 9003_0014 / 9003_8014
The Direct Mode RX Data FIFO register is used when in direct mode of operation, to
read the RX Data FIFO.
Note:
The Module Direct Mode RX FIFO Status register must be read before this
register is read, to determine the valid number of bytes in the 32-bit access.
The data is packed in little endian format.
Register
Register bit
assignment
Bit(s) Access Mnemonic Reset Description
D31:12 N/A Reserved N/A N/A
D11:09 R BYTE N/A Number of bytes in the current 32-bit location.
D08 N/A Reserved N/A N/A
D07 R FFLAG N/A Full flag
Indicates that the FIFO went full when the current
location was written.
D06:00 R PSTAT N/A General peripheral status, unique to the peripheral
attached to the channel.
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
RXD
RXD
Bit(s) Access Mnemonic Reset Description
D31:00 R RXD N/A RX Data FIFO Read register