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WORKING WITH THE CPU
R1: Control register
90 Hardware Reference NS9215
ICache and
DCache behavior
The M, C, I, and RR bits directly affect ICache and DCache behavior, as shown:
If either the DCache or ICache is disabled, the contents of that cache are not
accessed. If the cache subsequently is re-enabled, the contents will not have
changed. To guarantee that memory coherency is maintained, the DCache must be
cleaned of dirty data before it is disabled.
[6:3] N/A Reserved. SHOULD BE ONE.
[2] C bit DCache enable/disable
0 Cache disabled
1 Cache enabled
[1] A bit Alignment fault enable/disable
0 Data address alignment fault checking disabled
1 Data address alignment fault checking enabled
[0] M bit MMU enable/disable
0Disabled
1 Enabled
Bits Name Function
Cache MMU Behavior
ICache disabled Enabled or disabled All instruction fetches are from external memory (AHB).
ICache enabled Disabled All instruction fetches are cachable, with no protection
checking. All addresses are flat-mapped; that is:
VA=MVA=PA.
ICache enabled Enabled Instruction fetches are cachable or noncachable, and
protection checks are performed. All addresses are
remapped from VA to PA, depending on the MMU page
table entry; that is, VA translated to MVA, MVA
remapped to PA.
DCache disabled Enabled or disabled All data accesses are to external memory (AHB).
DCache enabled Disabled All data accesses are noncachable nonbufferable. All
addresses are flat-mapped; that is, VA=MVA=PA.
DCache enabled Enabled All data accesses are cachable or noncachable, and
protection checks are performed. All addresses are
remapped from VA to PA, depending on the MMU page
table entry; that is, VA translated to MVA, MVA
remapped to PA.