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8 Hardware Reference NS9215
Access instructions ....................................................................103
Register format ........................................................................103
Performing a fast context switch ...................................................103
Context ID register ....................................................................104
Access instructions ....................................................................104
Register format ........................................................................104
R14 register....................................................................................104
R15: Test and debug register ...............................................................104
Jazelle(Java) ..................................................................................104
DSP..............................................................................................105
MemoryManagement Unit (MMU)...........................................................105
MMU Features ..........................................................................105
Access permissions and domains ....................................................106
Translated entries .....................................................................106
MMU program accessible registers ..................................................107
Address translation ....................................................................107
Translation table base ................................................................108
TTB register format ...................................................................108
Table walk process ....................................................................109
First-level fetch........................................................................109
First-level fetch concatenation and address ......................................110
First-level descriptor..................................................................110
Page table descriptors ................................................................110
First-level descriptor bit assignments: Priority encoding of fault status .....111
First-level descriptor bit assignments: Interpreting first level descriptor bits
[1:0]..................................................................................111
Section descriptor .....................................................................111
Section descriptor format ............................................................111
Section descriptor bit description...................................................112
Coarse page table descriptor ........................................................112
Coarse page table descriptor format ...............................................112
Coarse page table descriptor bit description......................................112
Fine page table descriptor ...........................................................112
Fine page table descriptor format ..................................................113
Fine page table descriptor bit description.........................................113
Translating section references ......................................................113
Second-level descriptor...............................................................114
Second-level descriptor format .....................................................114
Second-level descriptor pages.......................................................114
Second-level descriptor bit assignments ...........................................115
Second-level descriptor least significant bits .....................................115
Translation sequence for large page references..................................116
Translating sequence for small page references .................................117
Translation sequence for tiny page references ...................................118
Subpages ................................................................................118