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222
Memory banks constructed from 16-or 32-bit memory devices................ 223
Dynamic memory controller................................................................ 225
Write protection ...................................................................... 225
Access sequencing and memory width............................................. 225
SDRAM Initialization ......................................................................... 225
Left-shift value table: 32-bit wide data bus SDRAM (RBC) ..................... 226
Left-shift value table: 32-bit wide data bus SDRAM (BRC) ..................... 227
Left-shift value table: 16-bit wide data bus SDRAM (RBC) ..................... 227
Left-shift value table: 16-bit wide data bus SDRAM (BRC) ..................... 228
SDRAM address and data bus interconnect .............................................. 228
32-bit wide configuration............................................................ 228
32-bit wide configuration............................................................ 229
Registers ...................................................................................... 230
Register map........................................................................... 230
Reset values ........................................................................... 232
Control register .............................................................................. 232
Status register................................................................................ 234
Configuration register....................................................................... 234
Dynamic Memory Control register......................................................... 235
Dynamic Memory Refresh Timer register................................................. 236
Register................................................................................. 237
Dynamic Memory Read Configuration register .......................................... 237
Dynamic Memory Precharge Command Period register ................................ 238
Dynamic Memory Active to Precharge Command Period register .................... 239
Dynamic Memory Self-refresh Exit Time register ....................................... 240
Dynamic Memory Last Data Out to Active Time register .............................. 240
Dynamic Memory Data-in to Active Command Time register ......................... 241
Dynamic Memory Write Recovery Time register ........................................ 242
Dynamic Memory Active to Active Command Period register......................... 243
Dynamic Memory Auto Refresh Period register ......................................... 243
Dynamic Memory Exit Self-refresh register .............................................. 244
Dynamic Memory Active Bank A to Active Bank B Time register ..................... 245
Dynamic Memory Load Mode register to Active Command Time register........... 246
Static Memory Extended Wait register ................................................... 247
Example ................................................................................ 247
Dynamic Memory Configuration 0–3 registers ........................................... 247
Address mapping for the Dynamic Memory Configuration registers........... 249
Chip select and memory devices ................................................... 250
Dynamic Memory RAS and CAS Delay 0–3 registers ..................................... 250
StaticMemory Configuration 0–3 registers................................................ 251
StaticMemory Write Enable Delay 0–3 registers......................................... 254
Static Memory Output Enable Delay 0–3 registers ...................................... 255
Static Memory Read Delay 0–3 registers.................................................. 256
StaticMemory Page Mode Read Delay 0–3 registers..................................... 256