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MEMORY CONTROLLER
Dynamic Memory Active Bank A to Active Bank B Time register
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Register
Register bit
assignment
Dynamic Memory Active Bank A to Active Bank B Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
register
Address: A070 0054
The Dynamic Memory Active Bank A to Active Bank B Time register allows you to
program the active bank A to active bank B latency, t
RRD
. It is recommended that
this register be modified during system initialization, or when there are no current
or outstanding transactions. Wait until the memory controller is idle, then enter
low-power or disabled mode. This value normally is found in SDRAM datasheets as
t
RRD
.
Note:
The Dynamic Memory Active Bank A to Active Bank B Time register is used for
all four dynamic memory chip selects. The worst case value for all chip
selects must be programmed.
Register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved XSR
Bits Access Mnemonic Description
D31:05 N/A Reserved N/A (do not modify)
D04:00 R/W XSR Exit self-refresh to active time command
0x0–0x1E
n+1 clock cycles, where the delay is in clk_out cycles
0x1F
32 clock cycles (reset value on reset_n)
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved RRD