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I/O HUB MODULE
[Module] DMA TX Control
380 Hardware Reference NS9215 31 March 2008
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[ Module] DMA TX Control
Addresses: 9000_0018 / 9000_8018 / 9001_0018 / 9001_8018 / 9002_0018 /
9002_8018 / 9003_0018
The DMA TX Control register contains control register settings for each transmit DMA
channel.
Register
Register bit
assignment
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
INDEX
CA
DIRECT
CE
FLEX
I/O
INDEXEN
Reserved
STATE
Bit(s) Access Mnemonic Reset Description
D31 R/W CE 0x0 Channel enable
0 Disable DMA operation
1 Enable DMA operation
D30 R/W CA 0x0 Channel abort
When set, causes the current DMA operation to
complete and closes the buffer. The DMA channel
remains idle until this bit is cleared.
D29 R/W FLEX I/O 0x0 0 DMA controlled by CPU
1 DMA controlled by flexible I/O module
This bit is valid only for channels 0 and 1, which
are assigned to flexible I/O module 0 and flexible
I/O module 1.
D28 R/W DIRECT 0x0 0 DMA mode
1 Direct access mode
D27 R/W INDEXEN 0x0 0 Hardware will not use the INDEX field when
in the idle state
1 Hardware will use the INDEX field when in
the idle state
D26:16 N/A Reserved N/A N/A
D15:10 R STATE 0x0 DMA state machine status field
D09:00 R/W INDEX 0x0 When the state machine is in the idle state, this
register can be used to change the index. This field
can be read at any time to determine the current
index.