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ETHERNET COMMUNICATION MODULE
MII Management Command register
296 Hardware Reference NS9215
Clocks field
settings
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MII Management Command register
Address: A060 0424
D04:02 R/W CLKS 0x0 Clock select
Used by the clock divide logic in creating the MII
management clock, which (per the IEEE 802.3u
standard) can be no faster than 2.5 MHz.
Note: Some PHYs support clock rates up to 12.5
MHz.
The AHB bus clock is used as the input to the clock
divide logic. See the “Clocks field settings” table for
settings that can be used with AHB clock (hclk)
frequencies.
D01 R/W SPRE 0 Suppress preamble
0 Causes normal cycles to be performed
1 Causes the MII Management module to perform
read/write cycles without the
32-bit preamble field. (Preamble suppression is
supported by some PHYs.)
D00 R/W Not used 0 Always write to 0.
Bits Access Mnemonic Reset Description
CLKS field Divisor AHB bus clock for 2.5 MHz
(max) MII management clock
AHB bus clock for 12.5 MHz
(max) MII management clock
000 4
001 4 37.5 MHz
010 6 74.9 MHz
011 8
100 10
101 20 37.5 MHz
110 30 74.9 MHz
111 40