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MEMORY CONTROLLER
StaticMemory Turn Round Delay 0–3 registers
258 Hardware Reference NS9215
Register
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
StaticMemory Turn Round Delay 0–3 registers
Address: A070 0218 / 0238 / 0258 / 0278
The Static Memory Turn Round Delay 0–3 registers allow you to program the number
of bus turnaround cycles. It is recommended that these registers be modified during
system initialization, or when there are no current or outstanding transactions. Wait
until the memory controller is idle, then enter low-power or disabled mode.
Register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved WTWR
Bits Access Mnemonic Description
D31:05 N/A Reserved N/A (do not modify)
D04:00 R/W WTWR Write wait states (WAITWR)
00000–11110 (n+2)
clk_out cycle write access time. The wait
state time for write accesses after the first read is WAITWR
(n+2) x t
clk_out
11111 332 clk_out cycle write access time (reset value on reset_n)
SRAM wait state time for write accesses after the first read.
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved WTTN