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MEMORY CONTROLLER
StaticMemory Write Enable Delay 0–3 registers
254 Hardware Reference NS9215
Note:
Synchronous burst mode memory devices are not supported.
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StaticMemory Write Enable Delay 0–3 registers
Address: A070 0204 / 0224 / 0244 / 0264
The Static Memory Write Enable Delay 0–3 registers allow you to program the delay
from the chip select to the write enable assertion. The Static Memory Write Enable
Delay register is used in conjunction with the Static Memory Write Delay registers,
to control the width of the write enable signals. It is recommended that these
registers be modified during system initialization, or when there are no current or
outstanding transactions. Wait until the memory controller is idle, then enter low-
power or disabled mode.
Register
D02 R/W BMODE Burst mode
Allows the static output enable signal to toggle during bursts.
0 Do not toggle output enable during bursts
1 Toggle output enable during bursts
D01:00 R/W MW Memory width
00 8 bit (reset value for chip select 0, 2, and 3 on
reset_n)
01 16 bit
10 32 bit
11 Reserved
The value of the chip select 1 memory width field on power-on
reset (
reset_n) is determined by the gpio_a[0], addr[23] signal. This
value can be overridden by software.
Note: For chip select 1, the value of the gpio_a[0], addr[23] signal
is reflected in this field. When programmed, this register
reflects the last value written into it.
Bits Access Mnemonic Description
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved WWEN