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SYSTEM CONTROL MODULE
Vectored interrupt controller (VIC) flow
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Vectored interrupt controller (VIC) flow
This is how the VIC flow works:
1 An interrupt occurs.
2 The CPU branches to either the IRQ or FIQ interrupt vector.
3 If the CPU goes to the IRQ vector, the CPU reads the service routine address from
the VIC’s ISADDR register. The READ updates the VIC’s priority hardware to
prevent current or any lower priority interrupts from interrupting again. The
CPU must not read the ISADDR register for FIQ interrupts.
4 The CPU branches to the Interrupt Service Routine (ISR) and stacks the
workspace so the IRQ can be enabled.
5 The CPU enables the IRQ interrupts so higher priority interrupts can be serviced.
6 The CPU executes the interrupt service routine.
7 The CPU clears the source of the current interrupt.
8 The CPU disables the IRQ and restores the workspace.
9 If IRQ, the CPU writes the level value of the interrupt being serviced to the
ISADDR register to clear the current interrupt path in the VIC’s priority
hardware.
10 The CPU returns from the interrupt.
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Configurable system attributes
System software can configure these system attributes:
Little endian/big endian mode
Watchdog timer enable
Watchdog timeout generates IRQ/FIQ/RESET
Watchdog timeout interval
Enable/disable ERROR response for misaligned data access
System module clock enables
Enable access to internal registers in USER mode
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PLL configuration
Hardware strapping determines the initial powerup PLL (see “Bootstrap
initialization” on page 152). After powerup, software can change the PLL settings
by writing to the PLL Configuration register.