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WORKING WITH THE CPU
R8:TLB Operations register
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Note:
The test and clean DCache instruction MRC p15, 0, r15, c7, c10, 3 is a special
encoding that uses
r15 as a destination operand. The PC is not changed by
using this instruction, however. This
MRC instruction also sets the condition
code flags.
If the cache contains any dirty lines, bit 30 is set to 0. If the cache contains no dirty
lines, bit 30 is set to 1. Use the following loop to clean the entire cache:
tc_loop: MRC p15, 0, r15, c7, c10, 3; test and clean
BNE tc_loop
Test, clean, and
invalidate DCache
instruction
The test, clean, and invalidate DCache instruction is the same as the test and clean
DCache instruction except that when the entire cache has been cleaned, it is
invalidated. Use the following loop to test, clean, and invalidate the entire DCache:
tci_loop: MRC p15, 0, r15, c7, c14, 3; test clean and invalidate
BNE tci_loop
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R8:TLB Operations register
Register R8 is a write-only register that controls the translation lookaside buffer
(TLB). There is a single TLB used to hold entries for both data and instructions. The
TLB is divided into two parts:
Set-associative
Fully-associative
The fully-associative part (also referred to as the lockdown part of the TLB) stores
entries to be locked down. Entries held in the lockdown part of the register are
preserved during an invalidate-TLB operation. Entries can be removed from the
lockdown TLB using an invalidate TLB single entry operation.
TLB operations There are six TLB operations; the function to be performed is selected by the
opcode_2 and CRm fields in the MCR instruction used to write register R8. Writing
other
opcode_2 or CRm values is UNPREDICTABLE. Reading from this register is
UNPREDICTABLE.
TLB operation
instructions
Use these instruction to perform TLB operations.
Operation Data Instruction
Invalidate set-associative TLB SBZ
MCR p15, 0, Rd, c8, c7, 0
Invalidate single entry SBZ
MCR p15, 0, Rd, c8, c7. 1
Invalidate set-associative TLB SBZ
MCR p15, 0, Rd, c8, c5, 0
Invalidate single entry MVA
MCR p15, 0, Rd, c8, c5, 1