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SERIAL CONTROL MODULE: HDLC
HDLC Data register 3
428 Hardware Reference NS9215
Register
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDLC Data register 3
Address: 9002_9108
HDLC Data Register 3 writes the last byte of data of a frame after which the closing
flag is transmitted. This register is for debug purposes only.
Register
Register bit
assignment
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved HDATA
Reserved
Bits Access Mnemonic Reset Description
D31:08 N/A Reserved N/A N/A
D07:00 R/W HDATA 0 Read Returns the contents of the receive buffer
Write Used for the last data byte in a frame, after which
the CRC and closing flag are transmitted
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved HDATA
Reserved
Bits Access Mnemonic Reset Description
D31:08 N/A Reserved N/A N/A
D07:00 R/W HDATA 0 Read Returns the contents of the receive buffer
Write Used for the last data byte in a frame, after which
the closing flag is transmitted