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SERIAL CONTROL MODULE: UART
Interrupt Status register
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Interrupt Status register
Address: 9001_1008 / 9001_9008 / 9002_1008 / 9002_9008
The Interrupt Status register provides status about UART events. All events are
indicated by reading a 1 and are cleared by writing a 1.
D06 R/W DCD 0 Enable data carrier
Enables interrupt generation whenever a stat change
occurs on input signal DCD.
D05 R/W CTS 0 Enable clear to send
Enables interrupt generation whenever a state change
occurs on input signal CTS.
D04 R/W RI 0 Enable ring indicator
Enables interrupt generation whenever a state change
occurs on input signal RI.
D03 R/W TBC 0 Enable transmit buffer close
Enables interrupt generation when the UART transmit
FIFO indicates to the UART transmitter that a byte
corresponds to a buffer close event.
D02 R/W RBC 0 Enable receive buffer close
Enables interrupt generation whenever a buffer close event
is passed from the UART receiver to the receive FIFO.
These are the UART receive buffer close events:
1 Receive character match
2 Receive character gap timeout
3 Receive line break
4 Receive framing error
5 Receive parity error
D01 R/W TX_IDLE 0 Enable transmit idle
Enables interrupt generation whenever the transmitter
moves from the active state to the idle state. This indicates
that the transmit FIFO is empty and the transmitter is not
actively shifting out data.
D00 R/W RX_IDLE 0 Enable receive idle
Enables interrupt generation whenever the receiver moves
from the active state to the idle state. If a start bit is not
received after a stop bit, the receiver enters the idle state.
Bits Access Mnemonic Reset Description