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TIMING
Memory Timing
www.digiembedded.com 489
SDRAM burst
read (32 bit), CAS
latency = 3
Notes:
1 This is the bank and RAS address.
2 This is the CAS address.
pre act read lat lat data-A data-B data-C data-D
M9
M8
M7
M6
M5
M11M4
M2
M1
Note-1 Note-2
clk_out
data<31:0>
addr
data_mask<3:0>*
dy_cs_n<3:0>*
ra s_n
cas_n
we_n