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SERIAL CONTROL MODULE: UART
Receive Character GAP Control register
398 Hardware Reference NS9215
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Receive Character GAP Control register
Address: 9001_100C / 9001_900C / 9002_100C / 9002_900C
The Receive Character GAP Control register configures the receive character gap
control logic.
Register REGISTER
Register bit
assignment
D01 R/W1TC TX_IDLE 0 Transmit idle
Indicates that the transmitter has moved from the active
state to the idle state. The transmitter moves from the active
state to the idle state when the transmit FIFO is empty and
the transmitter is not actively shifting out data.
D00 R/W1TC RX_IDLE 0 Receive idle
Indicates that the receiver has moved from the active state
to the idle state. The receiver moves from the active state to
the idle state when a start bit has not been received after the
previous stop bit.
Bits Access Mnemonic Reset Description
Bits Access Mnemonic Reset Description
D31 R/W ENABLE 0 Enable receive character gap timer
Write a 1 to this field to enable the receive character gap
timer.
D30:25 R/W Not used 0x0 Write this field to 0.
D24:00 R/W VALUE 0 Value
Defines the period between receiving the stop bit and
asserting the character gap timeout event.
Use this equation to compute the required divisor value:
N = ((FCLK * gap+period) - 1)
F
CLK
= Nominal 29.4912 MHz
gap_period = Desired character gap period
A reasonable setting is 10 bit periods one character plus
the start and stop bits. Given a data rate of 115,200bps, the
desired period is 86.8us and the timeout value is 2559
d
.